This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on patent application Nos. 092123496 filed in TAIWAN on Aug. 26, 2003, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a combination circuit for detecting the layout in a flat panel with thin film transistor processed during array manufacturing process. This method conducts in a prior art short-ring layout and shorting-bar layout so that the designing of the panel layout will not limited to the detection facility so as to promote the yield and reduce the cost.
2. Description of the Prior Art
Presently, after the liquid crystal display (LCD) panel is manufactured, a detection process is required to detect whether the operation of each of the thin film transistors in the display panel for controlling the pixel display is correct or not. The detection circuit layout surrounding the panel has to meet the form of the detection facility. The commonly applied detection circuit layout comprises the short-ring layout and the shorting-bar layout.
Because the layouts for the two facilities are different, the masks for the manufacturing processes are different so as to make it difficult to meet the yield of the array manufacturing process. Usually, because the types of the layouts designed by the panel manufacturers are different, such as the different sizes, resolutions, different array detection facilities have to be switched. This makes the panel design troublesome and increases the cost for buying the detection facility in order to meet different types of the layouts. The following is the detailed description for the two types of layouts.
Please refer to FIG. 1A. FIG. 1A is a perspective diagram of a circuit of a prior art with short-ring layout. The figure shows a display device with array layout for a liquid crystal display panel. The panel is formed by pulling a plurality of scan lines 13 and data lines 14 from a gate driver G and a data driver D to be interlaced and vertical to each other. The thin film transistors 11 for controlling the pixel display are positioned on the interlaced portions of the scan lines 13 and the data lines 14. The scan lines 13 processes storage capacitances 12 which is constructed with CS ON GATE manner. The pixel display is controlled by the charging/discharging of the storage capacitances 12. In order to detect the correctness of the devices connected to the thin film transistors 11 and the surrounding layout, the plurality of scan lines 13 and the data lines 14 are connected to the external detection facility. As shown in the figure, the plurality of scan lines 13 are connected to a plurality of gate end contact pads 15a, and the plurality of data lines 14 are connected to a plurality of data end contacting polar plates 15b. The plurality of contact pads 15a, 15b are IC signal inputting points for being the positions to be in touch with the probe of the detection facility so as to detect whether each of the display device is fine. The plurality of gate end contact pads 15a and the data end contact pads 15b are connected to the shorting-ring 17 via a plurality of resistances 16. The detected data Of each display devices from probe is contacted so as to determine the yield. After accomplishing the detection for the panel, the next manufacturing process is performed. By cutting along the direction of the panel cutting line 18, the next step of the manufacturing process is continued.
As shown in FIG. 1B, which is a perspective diagram of a partial circuit of the prior art with short-ring layout, the scan lines 13 or the data lines 14 are connected to a plurality of contact pads 15a, 15b. The probe 19 of the detection facility is in touch with the contact pads 15a, 15b. By using the resistances 16, the larger static electricity is spread to each of the scan lines 13 or the data lines 14 so as to prevent the panel pixel from being damaged by the static electricity.
Please refer to FIG. 2A. FIG. 2A is a perspective diagram of a circuit of a prior art with shorting-bar layout. As FIG. 1A, FIG. 2A shows a display device array layout for a liquid crystal display panel. The panel is formed by pulling out a plurality of scan lines 13 and the data lines 14 from the gate driver G and the data driver D to be vertically interlaced. The thin film transistors 11 for controlling the pixel display are positioned on the interlaced portions. The pixel display is controlled by the charging/discharging of the storage capacitances 12. The detection method for the shorting-bar layout does not apply the probe detection. In order to detect the correctness of the devices connected to thin film transistors 11 and the surrounding layout, the plurality of scan lines 13 and the data lines 14 separately have the circuits to be connected to the external detection facility. As show in the figure, the plurality of scan lines 13 are connected to the plurality of gate end contact pads 15a, and the plurality of data lines 14 are connected to the plurality of data end contact pads 15b. The plurality of polar plates 15a, 15b are separately connected to a plurality of short-ring of the external substrate circuit. The neighboring two contact pads are separately connected to the different short-ring.
As shown in the figure, the gate end contact pads 15a are the plurality of contact pads connected to the scan lines 13 of the gate driver G in the panel. The neighboring two contact pads are separately connected to the odd gate line 23 and the even gate line 24. The terminals are separately connected to the odd gate end G1 and the even gate end G2. Similarly, the data lines 14 are connected to the plurality of data end contact pads 15b. The neighboring contact pads are separately connected to the odd data line 21 and the even data line 22. The terminals of the conducting wires are connected to the odd data end D1 and the even data end D2. The circuit of this shorting-bar layout applies the odd data end D1, the even data end D2, the odd gate end G1 and the even gate end G2 for inputting the signals to the pixels so as to detect whether the display device inside the panel is operated well. After the detection for the panel is accomplished, by cutting along the direction of the panel division line 18, the next step of the manufacturing process is continuously performed.
Please refer to FIG. 2B. FIG. 2B is a perspective diagram of a partial circuit of the prior art shorting-bar layout. FIG. 2B is a partial circuit of the gate driver G in FIG. 2A. The plurality of scan lines 13 are connected to the plurality of gate end contact pads 15a. The neighboring two contact pads form odd/even contact pads distributions to be separately connected to the odd gate line 23 and the even gate line 24. The odd gate end G1 and the even gate end G2 are positioned on the terminals to be separately connected to the detection signals transmitted by the odd end contact pads and the even end contact pads. When practically carrying out, it is not limited to separate the circuit into two banks. In order to increase the efficiency of the detection, the circuit can be separated into a plurality of banks. Therefore, a plurality of conducting wires are positioned for transmitting a plurality of banks of contact pads signals to the terminals for detection.
The two mentioned prior art detection methods are different, and therefore, the layout design for the panel will be different because of the usage of the different detection methods, and the layout will be limited. In addition, because of the different layouts, the different masks have to be switched and bought so as to increase the cost. Therefore, the present invention combines the two detection circuits, and therefore, the prior art with short-ring layout and the shorting-bar layout can be conducted into the manufacturing process so that the designing of the panel layout will not be limited to the detection facility. Besides, the advantages and the disadvantages of the different detection methods can be compared so that the suggestions can be provided to the facility manufacturer for improvement. Therefore, the yield can be increased and the cost can be reduced.